module Mux4(
    input [31:0] MUXin0,
    input [31:0] MUXin1,
    input [31:0] MUXin2,
    input [31:0] MUXin3,
    input [1:0] MUXctrl0to3,
    output reg [31:0] MUXout
);

    initial begin
        MUXout <= 32'd0;
    end

    always @(*) begin
        if (MUXctrl0to3 == 2'b00)
            MUXout = MUXin0;
        else if (MUXctrl0to3 == 2'b01)
            MUXout = MUXin1;
        else if (MUXctrl0to3 == 2'b10)
            MUXout = MUXin2;
        else if (MUXctrl0to3 == 2'b11)
            MUXout = MUXin3;
        else
            MUXout = MUXin0;
    end

endmodule
